Conventionally, there is known an active matrix-type display device in which a plurality of gate bus lines (scanning signal lines) and a plurality of source bus lines (video signal lines) are arranged in a grid pattern and a plurality of pixel formation portions are arranged in a matrix form at the respective intersections of the plurality of gate bus lines and the plurality of source bus lines. Each pixel formation portion includes a TFT (Thin Film Transistor) which is a switching element connected at its gate terminal to a gate bus line passing through a corresponding intersection, and connected at its source terminal to a source bus line passing through the intersection; a pixel capacitance for holding a pixel value; and the like. The active matrix-type display device is also provided with a gate driver (scanning signal line drive circuit) that drives the plurality of gate bus lines, and a source driver (video signal line drive circuit) that drives the plurality of source bus lines.
A video signal indicating a pixel value is transmitted through a source bus line, and each source bus line cannot transmit video signals indicating pixel values for a plurality of rows at a time (at the same time). Therefore, writing of video signals to the pixel capacitances in the above-described pixel formation portions arranged in a matrix form is sequentially performed row by row. Hence, in order that the plurality of gate bus lines can be sequentially selected for a predetermined period, the gate driver is composed of a shift register including a plurality of stages.
FIG. 8 is a block diagram showing an exemplary configuration of a shift register 810 included in a conventional gate driver (see Published Japanese Translation of PCT Application No. 6-505605). As shown in FIG. 8, the gate driver is composed of the n-stage shift register 810. Each stage of the shift register 810 is a bistable circuit which is in either one of two states (a first state and a second state) at each time point and outputs a signal (state signal) indicating the state, as a scanning signal GOUT. As such, the shift register 810 is composed of n bistable circuits SR(1) to SR(n). To the shift register 810 are provided three-phase clock signals GCK1, GCK2, and GCK3 and a gate start pulse signal GSP which is a signal for starting scanning of gate bus lines. Each bistable circuit is provided with an input terminal for receiving any one of the three-phase clock signals as a first clock CKA; an input terminal for receiving any one of the three-phase clock signals as a second clock CKB; an input terminal for receiving the gate start pulse signal GSP or a state signal OUT outputted from its previous stage, as a set signal SET; and an output terminal for outputting a state signal OUT.
FIG. 9 is a circuit diagram showing an exemplary configuration of one stage (one bistable circuit) of the above-described conventional shift register 810. The bistable circuit includes six thin film transistors T81 to T86 and a capacitor C81. In addition, the bistable circuit has input terminals for a power supply line VDD which supplies a relatively high-level potential VGH and input terminals for a power supply line VSS which supplies a relatively low-level potential VGL, and three input terminals 81 to 83 and one output terminal 89. Note that the input terminal that receives a first clock CKA is denoted by a reference numeral 81, the input terminal that receives a set signal SET is denoted by a reference numeral 82, and the input terminal that receives a second clock CKB is denoted by a reference numeral 83. Note also that the potential VGH corresponds to a potential that places a thin film transistor in a pixel formation portion in an on state, and the potential VGL corresponds to a potential that places the thin film transistor in an off state.
The gate terminal of the thin film transistor T81, the source terminal of the thin film transistor T82, and the drain terminal of the thin film transistor T83 are connected to one another. Note that a region (wiring line) where they are connected to one another is referred to as a “netA” for convenience's sake. In addition, the gate terminal of the thin film transistor T83, the gate terminal of the thin film transistor T84, the source terminal of the thin film transistor T85, and the drain terminal of the thin film transistor T86 are connected to one another. Note that a region (wiring line) where they are connected to one another is referred to as a “netB” for convenience's sake.
The thin film transistor T81 is connected at its gate terminal to the netA, connected at its drain terminal to the input terminal 81, and connected at its source terminal to the output terminal 89. The thin film transistor T82 is connected at its gate terminal to the input terminal 82, connected at its drain terminal to the power supply line VDD, and connected at its source terminal to the netA. The thin film transistor T83 is connected at its gate terminal to the netB, connected at its drain terminal to the netA, and connected at its source terminal to the power supply line VSS. The thin film transistor T84 is connected at its gate terminal to the netB, connected at its drain terminal to the output terminal 89, and connected at its source terminal to the power supply line VSS. The thin film transistor T85 is connected at its gate terminal to the input terminal 83, connected at its drain terminal to the power supply line VDD, and connected at its source terminal to the netB. The thin film transistor T86 is connected at its gate terminal to the input terminal 82, connected at its drain terminal to the netB, and connected at its source terminal to the power supply line VSS. The capacitor C81 is connected at its one end to the netA and connected at its other end to the output terminal 89.
In a configuration such as that described above, three-phase clock signals GCK1, GCK2, and GCK3 having waveforms shown in FIGS. 10A to 10C and a gate start pulse signal GSP having a waveform shown in FIG. 10D are provided to the shift register 810. Then, scanning signals GOUT(1) to GOUT(n) which sequentially go to a high level for one horizontal scanning period as shown in FIGS. 10E to 10G are outputted from the shift register 810.
With reference to FIGS. 9 and 11A to 11F, the operation of each stage (bistable circuit) of the shift register 810 will be described below. Note that FIGS. 11A to 11F show waveforms for the bistable circuit SR(1) of the first stage, and for the bistable circuits SR(2) to SR(n) of the second and subsequent stages, the same waveforms as those shown in FIGS. 11A to 11F appear delayed by one horizontal scanning period. In other words, the n bistable circuits SR(1) to SR(n) perform the same operation with the exception of timing. Accordingly, in the following, description will be made focusing only on the bistable circuit SR(1) of the first stage.
During the operation of the display device, a first clock CKA having a waveform shown in FIG. 11A is provided to the input terminal 81, and a second clock CKB having a waveform shown in FIG. 11B is provided to the input terminal 83. During periods before time point t0, the potentials of a set signal SET, a netA, and a state signal OUT are VGL and the potential of a netB is VGH.
When reaching time point t0, a pulse of the set signal SET is provided to the input terminal 82. Accordingly, the thin film transistors T82 and T86 are placed in an on state (conducting state). In addition, at time point t0, the potential of the second clock CKB provided to the input terminal changes from VGL to VGH. Accordingly, the thin film transistor T85 is placed in an on state. By the thin film transistor T82 being placed in an on state, the potential of the netA is brought to VGH and thus the thin film transistor T81 is placed in an on state. In addition, the thin film transistor T85 is placed in an on state and the thin film transistor T86 is also placed in an on state and thus a current flows from the drain terminal of the thin film transistor T85 to the source terminal of the thin film transistor T86. Hence, the potential of the netB is brought to VGL. Accordingly, the thin film transistors T83 and T84 are placed in an off state (non-conducting state). By the thin film transistor T83 being placed in an off state, the potential of the netA does not decrease during the period from t0 to t1.
The thin film transistor T81 is, as described above, placed in an on state at time point t0, but the potential of the first clock CKA provided to the input terminal 81 is VGL during the period from t0 to t1. Hence, the potential of the state signal OUT outputted from the output terminal 89 is maintained at VGL. At this time, a voltage with the magnitude “VGH-VGL” is applied between the gate and source of the thin film transistor T81 (between the two terminals of the capacitor C81).
When reaching time point t1, the potentials of the set signal SET and the second clock CKB change from VGH to VGL. Accordingly, the thin film transistors T82, T85, and T86 are placed in an off state. In addition, at time point t1, the potential of the first clock CKA changes from VGL to VGH. At this time, since the voltage between the gate and source of the thin film transistor T81 is maintained at “VGH-VGL” by the capacitor C81, the thin film transistor T81 is in an on state. In addition, a parasitic capacitance (not shown) is formed between the gate and drain of the thin film transistor T81. Due to the above, the drain potential of the thin film transistor T81 increases with an increase in potential at the input terminal 81, and thus, the potential of the netA further increases from VGH through the parasitic capacitance. As a result, a large voltage is applied to the gate terminal of the thin film transistor T81 and thus the potential of the state signal OUT increases to the potential VGH of the first clock CKA. Accordingly, a gate bus line connected to the output terminal 89 of the bistable circuit is placed in a selected state. Meanwhile, during the period from t1 to t2, since the thin film transistor T85 is in an off state, the potential of the netB is maintained at VGL. Hence, during this period, the thin film transistor T83 is maintained in an off state and thus the potential of the netA is also maintained. Note that for the increase in the potential of the netA at time point t1, the potential ideally increases to a level twice the VGH, but in practice the potential does not increase to the level twice the VGH due to the presence of the parasitic capacitances, resistances, etc., of the netA, the input terminal 81, the output terminal 89, and the thin film transistor T81.
When reaching time point t2, the potential of the first clock CKA changes from VGH to VGL. At time point t2, since the potential of the netA is higher than VGH, when the drain potential of the thin film transistor T81 decreases with a decrease in potential at the input terminal 81, a current flows from the source terminal to drain terminal of the thin film transistor T81. Accordingly, the potential at the output terminal 89, i.e., the potential of the state signal OUT, decreases to VGL. Accordingly, the gate bus line connected to the output terminal 89 of the bistable circuit is placed in a non-selected state. Note that during the period from t2 to t3, since the potential of the second clock CKB is VGL and thus the thin film transistor T85 is in an off state, the potential of the netB is maintained at VGL. Hence, during this period, the thin film transistor T83 is maintained in an off state and the potential of the netA is also maintained.
When reaching time point t3, the potential of the second clock CKB changes from VGL to VGH. Hence, the thin film transistor T85 is placed in an on state. Accordingly, the potential of the netB is brought to VGH and thus the thin film transistors T83 and T84 are placed in an on state. By the thin film transistor T83 being placed in an on state, the potential of the netA is brought to VGL and thus the thin film transistor T81 is placed in an off state. In addition, by the thin film transistor T84 being placed in an on state, the potential of the state signal OUT is maintained at VGL.
The operation such as that described above is sequentially performed at the n bistable circuits SR (1) to SR (n) such that the timing is delayed by one horizontal scanning period. Accordingly, in each frame period, n gate bus lines GL1 to GLn are sequentially placed in a selected state for one horizontal scanning period.
As another example, the case in which a shift register circuit disclosed in Japanese Patent Application Laid-Open No. 62-234298 is applied to a gate driver of a display device will be described with reference to FIGS. 12, 13, 14A to 14J, and 15A to 15D. FIG. 12 is a block diagram showing a configuration of a shift register 910 included in the gate driver. As shown in FIG. 12, the shift register 910 is composed of n bistable circuits SR(1) to SR(n). To the shift register 910 are provided two-phase clock signals GCK1 and GCK2 and a gate start pulse signal GSP which is a signal for starting scanning of gate bus lines. Each bistable circuit is provided with an input terminal for receiving either one of the two-phase clock signals as a first clock CKA; an input terminal for receiving the gate start pulse signal GSP or a state signal OUT outputted from its previous stage, as a set signal SET; and an output terminal for outputting a state signal OUT.
FIG. 13 is a circuit diagram showing a configuration of one stage (one bistable circuit) of the shift register 910. The bistable circuit includes six thin film. transistors T90 to T95 and a capacitor C90. In addition, the bistable circuit has input terminals for a power supply line VDD which supplies a relatively high-level potential VGH and input terminals for a power supply line VSS which supplies a relatively low-level potential VGL, and three input terminals 91 to 93 and one output terminal 99. Note that the input terminal that receives a set signal SET is denoted by a reference numeral 91, one of the input terminals that receive a first clock CKA is denoted by a reference numeral 92, and the other one of the input terminals that receive a first clock CKA is denoted by a reference numeral 93.
The source terminal of the thin film transistor T90, the gate terminal of the thin film transistor T91, and one end of the capacitor C90 are connected to one another. Note that a region (wiring line) where they are connected to one another is referred to as a “netA” for convenience's sake. In addition, the source terminal of the thin film transistor T93, the drain terminal of the thin film transistor T94, and the gate terminal of the thin film transistor T95 are connected to one another. Note that a region (wiring line) where they are connected to one another is referred to as a “netB” for convenience's sake. Furthermore, the source terminal of the thin film transistor T91, the drain terminal of the thin film transistor T92, the gate terminal of the thin film transistor T94, the drain terminal of the thin film transistor T95, and the other end of the capacitor C90 are connected to one another. Note that a region (wiring line) where they are connected to one another is referred to as a “netC” for convenience's sake.
The thin film transistor T90 is connected at its gate terminal to the input terminal 92, connected at its drain terminal to the input terminal 91, connected at its source terminal to the netA. The thin film transistor T91 is connected at its gate terminal to the netA, connected at its drain terminal to the power supply line VDD, and connected at its source terminal to the netC. The thin film transistor T92 is connected at its gate terminal to the input terminal 92, connected at its drain terminal to the netC, and connected at its source terminal to the power supply line VSS. The thin film transistor T93 is connected at its gate terminal to the input terminal 93, connected at its drain terminal to the power supply line VDD, and connected at its source terminal to the netB. The thin film transistor T94 is connected at its gate terminal to the netC and the output terminal 99, connected at its drain terminal to the netB, and connected at its source terminal to the power supply line VSS. The thin film transistor T95 is connected at its gate terminal to the netB, connected at its drain terminal to the netC, and connected at its source terminal to the power supply line VSS. The capacitor C90 is connected at its one end to the netA and connected at its other end to the netC.
In a configuration such as that described above, two-phase clock signals GCK1 and GCK2 having waveforms shown in FIGS. 14A and 14B and a gate start pulse signal GSP having a waveform shown in FIG. 14C are provided to the shift register 910. Then, scanning signals GOUT(1) to GOUT(n) which sequentially go to a high level for one horizontal scanning period as shown in FIGS. 14D to 14J are outputted from the shift register 910.
With reference to FIGS. 13, 14A to 14J, and 15A to 15D, the operation of each stage (bistable circuit) of the shift register 910 will be described below. Note that FIGS. 15A to 15D show waveforms for the bistable circuit SR (1) of the first stage, and for the bistable circuits SR (2) to SR (n) of the second and subsequent stages, the same waveforms as those shown in FIGS. 15A to 15D appear delayed by one horizontal scanning period. In other words, the n bistable circuits SR (1) to SR (n) perform the same operation with the exception of timing. Accordingly, in the following, description will be made focusing only on the bistable circuit SR (1) of the first stage.
During the operation of the display device, a first clock CKA having a waveform shown in FIG. 15A is provided to the input terminal 91. During periods before time point t0, the potentials of a set signal SET, a netA, and a state signal OUT are VGL.
When reaching time point t0, the potential of the first clock CKA changes from VGL to VGH. Accordingly, the thin film transistors T90, T92, and T93 are placed in an on state. By the thin film transistor T93 being placed in an on state, the potential of the netB increases to the potential VGH of the power supply line VDD and thus the thin film transistor T95 is placed in an on state. In addition, at time point t0, the potential of the set signal SET changes from VGL to VGH. Since, as described above, the thin film transistor T90 is placed in an on state, the potential of the netA increases to the potential VGH of the set signal SET. At this time, since the voltage between the gate and source of the thin film transistor T91 (between the two terminals of the capacitor C90) is “VGH-VGL”, the thin film transistor T91 is placed in an on state. However, since the thin film transistors T92 and T95 are in an on state, the potential at the output terminal 99 (the potential of the state signal OUT) is maintained at VGL.
When reaching time point t1, the potentials of the set signal SET and the first clock CKA change from VGH to VGL. Accordingly, the thin film transistors T90, T92, T93, and T95 are placed in an off state. At this time, the voltage between the gate and source of the thin film transistor T91 is maintained at “VGH-VGL” by the capacitor C90. Hence, the thin film transistor T91 is maintained in an on state. Here, since, as described above, the thin film transistors T92 and T95 are in an off state, a current does not flow between the drain and source of each of the thin film transistors T92 and T95 and thus the potential at the output terminal 99 increases to the potential VGH of the power supply line VDD. Accordingly, a gate bus line connected to the output terminal 99 of the bistable circuit is placed in a selected state.
When reaching time point t2, the potential of the first clock CKA changes from VGL to VGH. Accordingly, the thin film transistors T90, T92, T93, and T95 are placed in an on state. At this time, since the potential of the set signal SET is VGL, the potential of the netA decreases from VGH to VGL and thus the thin film transistor T91 is placed in an off state. In addition, since, as described above, the thin film transistors T92 and T95 are in an on state, charge accumulated in the netC flows through the power supply lines VSS via the thin film transistors T92 and T95 and thus the potential at the output terminal 99 decreases from VGH to VGL.
The operation such as that described above is sequentially performed at the above-described n bistable circuits SR(1) to SR(n) such that the timing is delayed by one horizontal scanning period. Accordingly, in each frame period, n gate bus lines GL1 to GLn are sequentially placed in a selected state for one horizontal scanning period.